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- 1 - rev. 1.2 november 2006 128m gddr sdram k4d261638i revision 1.2 november 2006 2m x 16bit x 4 banks graphic double data rate synchronous dram 128mbit gddr sdram notice information in this document is provided in relation to samsung products, and is subject to change without notice. nothing in this document shall be construed as granting any license, express or implied, by estoppel or otherwise, to any intellectual property rights in samsung products or technology. all information in this document is provided on as "as is" basis without guarantee or warranty of any kind. 1. for updates or additional information about sa msung products, contact your nearest samsung office. 2. samsung products are not intended for use in life support, critical care, me dical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmen tal procurement to which special terms or provisions may apply. * samsung electronics reserves the right to ch ange products or specification without notice.
- 2 - rev. 1.2 november 2006 128m gddr sdram k4d261638i revision history revision month year history 0.0 march 2005 - target spec - defined target specification 0.1 may 2005 - corrected typo. - added cl2 feature in ac characteristics. 1.0 august 2005 - finalized spec - deleted cl2.5 option 1.1 january 2006 - corrected typo. 1.2 november 2006 - corrected typo.
- 3 - rev. 1.2 november 2006 128m gddr sdram k4d261638i the k4d261638i is 134,217,728 bits of hyper synchronous data rate dynamic ram organized as 4 x 2,097,152 words by 16 bits, fab ri- cated with samsung ? s high performance cmos technology. synchronous features with data strobe allow extremely high performance up to 1gb/s/chip. i/o transactions are possible on both edge s of the clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications. ? 2.5v + 5% power supply for device operation ? 2.5v + 5% power supply for i/o interface ? sstl_2 compatible inputs/outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 2,3(clock) -. burst length (2, 4 and 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the positive going edge of the system clock ? differential clock input ? wrtie-interrupted by read function ? 2 dqs?s ( 1dqs / byte ) ? data i/o transactions on both edges of data strobe ? dll aligns dq and dqs transitions with clock transition ? edge aligned data & data strobe output ? center aligned data & data strobe input ? dm for write masking only ? auto & self refresh ? 32ms refresh period (4k cycle) ? lead free 66pin tsop-ii (rohs compliant) ? maximum clock frequency up to 250mhz ? maximum data rate up to 500mbps/pin for 2m x 16bit x 4 bank ddr sdram 2m x 16bit x 4 banks double data rate synchronous dram with bi-directional data strobe and dll * k4d261638i-tc is the leaded package part number. * for k4d261638i-lc50, vdd & vddq = 2.375v to 2.7v. part no. max freq. max data rate interface package k4d261638i-lc40 250mhz 500mbps/pin sstl_2 66pin tsop-ii k4d261638i-lc50 200mhz 400mbps/pin 1.0 features 2.0 ordering information 3.0 general description
- 4 - rev. 1.2 november 2006 128m gddr sdram k4d261638i 4.0 pin configuration (top view) pin description ck,ck differential clock input ba 0 , ba 1 bank select address cke clock enable a 0 ~a 11 address input cs chip select dq 0 ~ dq 15 data input/output ras row address strobe v dd power cas column address strobe v ss ground we write enable v ddq power for dq?s l(u)dqs data strobe v ssq ground for dq?s l(u)dm data mask nc no connection rfu reserved for future use 1 66 pin tsop(ii) (400mil x 875mil) 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 27 26 25 24 23 22 21 54 53 52 51 50 49 48 47 46 45 44 43 35 36 37 38 39 40 41 42 55 56 57 58 59 60 34 (0.65 mm pin pitch) 33 32 31 30 29 28 61 62 63 64 65 66 v dd dq 0 v ddq dq 1 dq 2 v ssq dq 3 dq 4 v ddq dq 5 dq 6 v ssq ba 0 cs ras cas we ldm v ddq dq 7 v dd a 3 a 2 a 1 a 0 ap/a 10 ba 1 nc ldqs nc nc nc v dd v ss dq 15 v ssq dq 14 dq 13 v ddq dq 12 dq 11 v ssq dq 10 dq 9 v ddq a 11 cke ck udm v ref v ssq dq 8 v ss a 4 a 5 a 6 a 7 a 8 a 9 nc udqs nc v ss ck nc nc
- 5 - rev. 1.2 november 2006 128m gddr sdram k4d261638i *1 : the timing reference point for the different ial clocking is the cross point of ck and ck . for any applications using the single ended clocking, apply v ref to ck pin. symbol type function ck, ck *1 input the differential system clock input. all of the inputs are sampled on the rising edge of the clock except dq?s and dm?s that are sampled on both edges of the dqs. cke input activates the ck signal when high and deactivates the ck signal when low. by deactivating the clock, cke low indicates the powe r down mode or self refresh mode. cs input cs enables the command decoder when low and di sabled the command decoder when high. when the command decoder is disabled, new co mmands are ignored but previous operations continue. ras input latches row addresses on the positiv e going edge of the ck with ras low. enables row access & precharge. cas input latches column addresses on the positive going edge of the ck with cas low. enables col- umn access. we input enables write operation and row precharge. latches data in starting from cas , we active. ldqs,udqs input/output data input and output are synchronized with both edge of dqs. for the x16, ldqs corresponds to the data on dq0-dq7 ; udqs corresponds to the data on dq8-dq15. ldm,udm input data in mask. data in is masked by dm latency=0 when dm is high in burst write. for the x16, ldm corresponds to the data on dq0-dq7 ; udm correspons to the data on dq8-dq15. dq 0 ~ dq 15 input/output data inputs/outputs are multiplexed on the same pins. ba 0 , ba 1 input selects which bank is to be active. a 0 ~ a 11 input row/column addresses are multiplexed on the same pins. row addresses : ra 0 ~ ra 11 , column addresses : ca 0 ~ ca 8 . v dd /v ss power supply power and ground for the input buffers and core logic. v ddq /v ssq power supply isolated power supply and ground for the ou tput buffers to provide improved noise immunity. v ref power supply reference voltage for inputs, used for sstl interface. nc/rfu no connection/ reserved for future use this pin is recommended to be left "no connection" on the device 5.0 input/output func tional description
- 6 - rev. 1.2 november 2006 128m gddr sdram k4d261638i 6.0 block diagram (2mbit x 16i/o x 4 bank) bank select timing register address register refresh counter row buffer row decoder col. buffer data input register serial to parallel 2mx16 2mx16 2mx16 2mx16 sense amp 2-bit prefetch output buffer i/o control column decoder latency & burst length programming register strobe gen. ck,ck addr lcke ck,ck cke cs ras cas we ldm ldmi ck,ck lcas lras lcbr lwe lwcbr lras lcbr ck, ck 32 16 16 lwe ldmi x16 dqi data strobe intput buffer dll udm
- 7 - rev. 1.2 november 2006 128m gddr sdram k4d261638i 7.1 power-up sequence 7.0 functional description ddr sdrams must be powered up and initialized in a predefined manner to prevent undefined operations. 1. apply power and keep cke at low state (all other inputs may be undefined) - apply v dd before v ddq . - apply v ddq before v ref & v tt 2. start clock and maintain stable condition for minimum 200us. 3. the minimum of 200us after stable power and clock(ck,ck ), apply nop and take cke to be high . 4. issue prechar ge command for all banks of the device. 5. issue a emrs command to enable dll *1 6. issue a mrs command to reset dll. the additional 200 clock cycles ar e required to lock the dll. * 1,2 7. issue precharge command for all banks of the device. 8. issue at least 2 or more auto-refresh commands. 9. issue a mode register set comm and with a8 to low to initialize the mode register. *1 the additional 200cycles of clock input is required to lock the dll after enabling dll. *2 sequence of 6&7 is regardless of the order. power up & initialization sequence command 0 12345678910111213141516171819 trp 2 clock min. precharge all banks 2nd auto refresh mode register set any command t rfc 1st auto refresh t rfc emrs mrs 2 clock min. dll reset ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ precharge all banks t rp inputs must be stable for 200us ~ ~ 200 clock min. ~ ~ 2 clock min. ck,ck * when the operating frequency is changed, dll reset should be required again. after dll reset again, the minimum 200 cycles of clock input is needed to lock the dll.
- 8 - rev. 1.2 november 2006 128m gddr sdram k4d261638i the mode register stores the data for co ntrolling the various operating modes of ddr sdram. it programs cas latency, addressing mode, burst length, test mode, dll reset a nd various vendor specific options to make ddr sdram useful for variety of different appli- cations. the default value of the mode r egister is not defined, therefore the mode register mu st be written after emrs setting for proper operation. the mode register is written by asserting low on cs , ras , cas and we (the ddr sdram should be in active mode with cke already high prior to writing into the mo de register). the state of address pins a 0 ~ a 11 and ba 0 , ba 1 in the same cycle as cs , ras , cas and we going low is written in the mode register. minimum two cl ock cycles are requested to complete the write operation in the mode register. the mode register contents can be changed using the same command and clock cycle requirements during opera- tion as long as all banks are in the idle state. the mode regi ster is divided into various fiel ds depending on functionality. the burst length uses a 0 ~ a 2 , addressing mode uses a 3 , cas latency(read latency from column address) uses a 4 ~ a 6 . a 7 is used for test mode. a 8 is used for dll reset. a 7, a 8 , ba 0 and ba 1 must be set to low for normal mrs operation. refer to the table for specific codes for various burst length, addressing modes and cas latencies. address bus mode register cas latency a 6 a 5 a 4 latency 0 0 0 reserved 0 0 1 reserved 010 2 011 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved burst length a 2 a 1 a 0 burst type sequential interleave 0 0 0 reserve reserve 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve burst type a 3 type 0 sequential 1 interleave *1 : rfu(reserved for future use) should stay "0" during mrs cycle. ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 rfu *1 0 rfu *1 dll tm cas latency bt burst length ba 0 a n ~ a 0 0mrs 1emrs dll a8 dll reset 0no 1yes test mode a 7 mode 0 normal 1test 7.2 mode register set(mrs) *1 : mrs can be issued only at all banks precharge state. *2 : minimum trp is required to issue mrs command. mrs cycle command ck, ck precharge nop nop mrs nop nop 2 01 5 34 8 67 any nop all banks command t rp t mrd =2 t ck nop
- 9 - rev. 1.2 november 2006 128m gddr sdram k4d261638i the extended mode register stores the data for enabling or disabling dll and selecting output driver strength. the default valu e of the extended mode register is not defi ned, therefore the extened mode register must be wr itten after power up for enabling or disab ling dll. the extended mode register is written by asserting low on cs , ras , cas , we and high on ba0(the ddr sdram should be in all bank precharge with cke already high prior to writing into the extende d mode register). the state of address pins a0, a2 ~ a5, a7 ~ a11 and ba1 in the same cycle as cs , ras , cas and we going low are written in the extended mode register. a1 and a6 are used for setting driver strength to normal, weak or matched impedance. two clock cycles are required to complete the write operation in the exte nded mode register. the mode register contents can be changed usin g the same command and clock cycle requirements during operation as long as all banks are in the idle state. a0 is used for dll e nable or disable. "high" on ba0 is used for emrs. all the other address pins except a0,a1,a6 and ba0 must be set to low for proper emrs operation. refer to the table for specific codes. a 0 dll enable 0 enable 1 disable ba 0 a n ~ a 0 0mrs 1emrs address bus extended *1 : rfu(reserved for future use) should stay "0" during emrs cycle. rfu *1 1 rfu *1 d.i.c rfu *1 d.i.c dll ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 mode register 7.3 extended mode register set(emrs) a6 a1 output driver impedence control 00 full 0 1 weak 11 matced
- 10 - rev. 1.2 november 2006 128m gddr sdram k4d261638i a burst write can be interrupted by a read command of any bank. the dq ? s must be in the high impedance state at least one clock cycle before the interrupting read data appear on the outputs to avoid data contention. when the read command is registered, any residual data from the burst write cycle mu st be masked by dm. the delay from the last data to read command (tcdlr) is required to avoid the data contention dram inside. data that are presented on the dq pins before the read command is initiated will actual ly be written to the memory. read command interrupting write can not be issued at the next clock ed ge of that of write command. cmd < burst length=8, cas latency=3 > nop write nop nop nop nop read nop nop dqs dq s din 0 din 1 din 2 din 3 din 4 din 5 dout 0 din 6 din 7 t wr t dqssmax dm 2 0 1 5 3 4 8 6 7 t wpres ck ck the following function established how a read command may interrupt a write burst and which input data is not written into the memory. 1. for read commands interrupting a write burst, the minimum writ e to read command delay is 2 cl ock cycles. the case where the write to read delay is 1 clock cycle is disallowed 2. for read commands interrupting a write burst, the dm pin must be used to mask the input data words whcich immediately preced e the interrupting read operation and the input data word which imm ediately follows the interrupting read operation 3. for all cases of a read interrupting a write, the dq and dqs bus es must be released by the driving chip (i.e., the memory co ntroller) in time to allow the buses to turn around before the ddr sdram drives them during a read operation. 4. if input write data is masked by the read co mmand, the dqs input is ignored by the ddr sdram. 5. refer to "3.3.2 burst write operation" t wpreh nop nop note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restri cted to recommended operating condition. exposure to higher than recommended voltage for extended pe riods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to vss v in , v out -0.5 ~ 3.6 v voltage on v dd supply relative to vss v dd -1.0 ~ 3.6 v voltage on v dd supply relative to vss v ddq -0.5 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 2.0 w short circuit current i os 50 ma 8.0 absolute maximum ratings 7.4 write interrupted by a read
- 11 - rev. 1.2 november 2006 128m gddr sdram k4d261638i recommended operating conditions(voltage referenced to v ss =0v, t a =0 to 65 c) note : 1. under all conditions v ddq must be less than or equal to v dd . 2. v ref is expected to equal 0.50*v ddq of the transmitting device and to track variations in the dc level of the same. peak to peak noise on the v ref may not exceed + 2% of the dc value. thus, from 0.50*v ddq , v ref is allowed + 25mv for dc error and an additional + 25mv for ac noise. 3. v tt of the transmitting device must track v ref of the receiving device. 4. v ih (max.)= v ddq +1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 5. v il (mim.)= -1.5v for a pulse width and it can not be greater than 1/3 of the cycle rate. 6. for any pin under test input of 0v < v in < v dd is acceptable. for all other pins that are not under test v in =0v. 7. for k4d261638i-lc50, v dd & v ddq = 2.375v to 2.7v. parameter symbol min typ max unit note device supply voltage v dd 2.375 2.50 2.625 v 1, 7 output supply voltage v ddq 2.375 2.50 2.625 v 1, 7 reference voltage v ref 0.49*v ddq - 0.51*v ddq v2 termination voltage v tt v ref -0.04 v ref v ref +0.04 v 3 input logic high voltage v ih v ref +0.15 - v ddq +0.30 v 4 input logic low voltage v il -0.30 - v ref -0.15 v 5 output logic high voltage v oh v tt +0.76 - - v i oh =-15.2ma output logic low voltage v ol --v tt -0.76 v i ol =+15.2ma input leakage current i il -5 - 5 ua 6 output leakage current i ol -5 - 5 ua 6 9.1 power & dc operating co nditions(sstl_2 in/out) 9.0 ac & dc operating conditions recommended operating conditions unless otherwise noted ( ta=0 to 65 c) note : 1. measured with output open. 2. current meassured at v dd (max). 3. refresh period is 32ms. parameter symbol test condition version unit note -40 -50 operating current (one bank active) i cc1 burst lenth=2 t rc t rc (min) i ol =0ma, t cc = t cc (min) 200 180 ma 1, 2 precharge standby current in power-down mode i cc2 p cke v il (max), t cc = t cc (min) 45 40 ma 1, 2 precharge standby current in non power-down mode i cc2 n cke v ih (min), cs v ih (min), t cc = t cc (min). 70 60 ma 1, 2 active standby current power-down mode i cc3 p cke v il (max), t cc = t cc (min) 85 70 ma 1, 2 active standby current in in non power-down mode i cc3 n cke vih(min), cs vih(min), t cc = t cc (min) . 135 110 ma 1, 2 operating current ( burst mode) i cc4 i ol =0ma , t cc = t cc (min), page burst, all banks ac tivated. 390 345 ma 1, 2 refresh current i cc5 t rc t rfc (min) 200 180 ma 1, 2,3 self refresh current i cc6 cke 0.2v 10 10 ma 1, 2 9.2 dc characteristics
- 12 - rev. 1.2 november 2006 128m gddr sdram k4d261638i recommended operating conditions(voltage referenced to v ss =0v, v dd =2.5v+ 5%, v ddq =2.5v+ 5%,t a =0 to 65 c) note : 1. v id is the magnitude of the difference between t he input level on ck and the input level on ck . 2. the value of v ix is expected to equal 0.5*v ddq of the transmitting device and must track variations in the dc level of the same. 3. for k4d261638i-lc50, v dd & v ddq = 2.375v to 2.7v. parameter symbol min typ max unit note input high (logic 1) voltage; dq v ih v ref +0.35 - - v input low (logic 0) voltage; dq v il --v ref -0.35 v clock input differential voltage; ck and ck v id 0.7 - v ddq +0.6 v 1 clock input crossing point voltage; ck and ck v ix 0.5*v ddq -0.2 - 0.5*v ddq +0.2 v 2 9.4 ac operating test conditions 9.3 ac input operating conditions r t =50 ? output c load =30pf (fig. 1) output load circuit z0=50 ? v ref =0.5*v ddq v tt =0.5*v ddq (vdd=2.5v+ 5% *2 , ta= 0 to 65 c) note : 1. in case of differential clocks(ck and ck ), input reference voltage for clock is a ck and ck ?s crossing point. 2. for k4d261638i-lc50, v dd & v ddq = 2.375v to 2.7v. parameter value unit note input reference voltage for ck(for single ended) 0.50*v ddq v1 ck and ck signal maximum peak swing 1.5 v ck signal minimum slew rate 1.0 v/ns input levels(v ih /v il )v ref +0.35/v ref -0.35 v input timing measurement reference level v ref v output timing measurement reference level v tt v output load condition see fig.1
- 13 - rev. 1.2 november 2006 128m gddr sdram k4d261638i decoupling capacitance guide line 9.5 capacitance recommended decoupling capacitance added to power line at board. 1. v dd and v ddq pins are separated each other. all v dd pins are connected in chip. all v ddq pins are connected in chip. 2. v ss and v ssq pins are separated each other. all v ss pins are connected in chip. all v ssq pins are connected in chip. parameter symbol value unit decoupling capacitance between v dd and v ss c dc1 0.1 + 0.01 uf decoupling capacitance between v ddq and v ssq c dc2 0.1 + 0.01 uf (vdd=2.5v, ta= 25 c, f=1mhz) parameter symbol min max unit input capacitance( ck, ck )c in1 1.0 5.0 pf input capacitance(a 0 ~a 11 , ba 0 ~ba 1 )c in2 1.0 4.0 pf input capacitance( cke, cs , ras ,cas , we )c in3 1.0 4.0 pf data & dqs input/output capacitance(dq 0 ~dq 15 )c out 1.0 6.5 pf input capacitance(dm0 ~ dm3) c in4 1.0 6.5 pf note 1 : - the jedec ddr specification currently defines the output data valid window(tdv) as the time period when the data strobe and all data associated with that data strobe are coincidentally valid. - the previously used definition of tdv( =0.35tck) artificially penalizes system timing budgets by assuming the worst case ou tput vaild window even then the clock duty cycle applied to the device is better than 45/55% - a new ac timing term, tqh which stands fo r data output hold time from dqs is difined to account for clock duty cycle variati on and replaces tdv - tqhmin = thp-x where . thp=minimum half clock period for any given cycle and is defined by clock high or clock low time(tch,tcl) . x=a frequency dependent timing allowance account for tdqsqmax parameter symbol -40 -50 unit note min max min max ck cycle time cl=2 tck 7.5 10 7.5 10 ns cl=3 tck 4.0 10 5.0 10 ns ck high level width tch 0.45 0.55 0.45 0.55 tck ck low level width tcl 0.45 0.55 0.45 0.55 tck dqs out access time from ck tdqsck -0.6 0.6 -0.7 0.7 ns output access time from ck tac -0.6 0.6 -0.7 0.7 ns data strobe edge to dout edge tdqsq - 0.4 - 0.45 ns 1 read preamble trpre 0.9 1.1 0.9 1.1 tck read postamble trpst 0.4 0.6 0.4 0.6 tck ck to valid dqs-in tdqss 0.85 1.15 0.8 1.2 tck dqs-in setup time twpres 0 - 0 - ns dqs-in hold time twpreh 0.35 - 0.3 - tck dqs write postamble twpst 0.4 0.6 0.4 0.6 tck dqs-in high level width tdqsh 0.4 0.6 0.4 0.6 tck dqs-in low level width tdqsl 0.4 0.6 0.4 0.6 tck address and control input setup tis 0.9 - 1.0 - ns address and control input hold tih 0.9 - 1.0 - ns dq and dm setup time to dqs tds 0.4 - 0.45 - ns dq and dm hold time to dqs tdh 0.4 - 0.45 - ns clock half period thp tclmin or tchmin - tclmin or tchmin -ns1 data output hold time from dqs tqh thp-0.4 - thp-0.45 - ns 1 9.6 ac characteristics
- 14 - rev. 1.2 november 2006 128m gddr sdram k4d261638i ac characteristics (ii)_continued note : 1. for normal write operation, even numbers of din are to be written inside dram. 2. trcdwr should be always greater or equal to 2tck. parameter symbol -40 -50 unit note min max min max row cycle time trc 52 - 55 - ns refresh row cycle time trfc 60 - 70 ns row active time tras 36 100k 40 100k ns ras to cas delay for read trcdrd 16 - 15 - ns ras to cas delay for write trcdwr 8 - 10 - ns 2 row precharge time trp 16 - 15 - ns row active to row active trrd 12 - 10 ns last data in to row precharge @normal precharge twr 3 - 3 - tck 1 last data in to row precharge @auto precharge twr_a 3 - 3 - tck 1 last data in to read command tcdlr 2 - 2 - tck 1 col. address to col. address tccd 1 - 1 - tck mode register set cycle time tmrd 2 - 2 - tck auto precharge write recovery + precharge tdal 7 - 6 - tck exit self refresh to read command txsr 200 - 200 - tck power down exit time tpdex 3tck+tis - 3tck+tis - ns refresh interval time tref - 7.8 - 7.8 us ac characteristics (iii)_continued (unit : number of clock) k4d261638f-lc40 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 250mhz ( 4.0ns ) 3 13 15 9 4 2 4 3 7 tck 200mhz ( 5.0ns ) 3 11 14 8 3 2 3 2 6 tck 133mhz ( 7.5ns ) 3 or 2 7 8 5 3 2 3 2 4 tck k4d261638f-lc50 frequency cas latency trc trfc tras trcdrd trcdwr trp trrd tdal unit 200mhz ( 5.0ns ) 3 11 14 8 3 2 3 2 6 tck 133mhz ( 7.5ns ) 3 or 2 8 10 6 2 2 2 2 4 tck
- 15 - rev. 1.2 november 2006 128m gddr sdram k4d261638i simplified timing @ bl=4 normal write burst (@ bl=4) multi bank interleaving write burst (@ bl=4) 012345678 13 14 15 16 17 18 19 20 21 9101112 22 com dqs dq we dm ck, ck a10/ap addr (a0~a9 ba[1:0] da0 da1 da2 da3 da0 da1 da2 da3 db0 db1 db2 db3 act_a wr_a prech act_a wr_a act_b wr_b t rcd t ras t rp t rc t rrd baa baa baa baa baa bab bab rb rb ca cb ra ra ra ca ra ,a11) 10.0 simplified timing
- 16 - rev. 1.2 november 2006 128m gddr sdram k4d261638i pulldown current (ma) pullup current (ma) voltage (v) minimum maximum minimum maximum 0.00000 0.1 1.368 1.716 -0.9 -0.924 0.2 4.968 6.996 -4.536 -6.424 0.3 8.46 12.32 -7.92 -11.572 0.4 11.808 17.512 -11.196 -16.588 0.5 14.904 22.616 -14.328 -21.472 0.6 17.892 27.544 -17.208 -26.136 0.7 20.376 32.12 -19.908 -30.756 0.8 22.716 36.564 -22.428 -35.024 0.9 24.624 40.612 -24.732 -39.204 1.0 26.208 44.176 -26.748 -42.988 1.1 27.432 47.388 -28.476 -46.508 1.2 28.224 50.028 -29.952 -49.808 1.3 28.836 52.184 -31.176 -52.668 1.4 29.268 53.81 2 -32.22 -55.22 1.5 29.592 55 -33.048 -57.464 1.6 29.808 55.88 -33.696 -59.356 1.7 29.988 56.54 -34.308 -60.896 1.8 30.168 56.98 -34.812 -62.172 1.9 30.348 57.332 -35.244 -63.272 2.0 30.456 57.64 -35.64 -64.24 2.1 30.564 57.86 -36 -65.032 2.2 30.708 58.08 -36.288 -65.736 2.3 30.78 58.256 -36.576 -66.352 2.4 30.807 58.388 -36.648 -66.924 2.5 30.879 58.52 -36.747 -67.452 2.6 30.924 58.652 -36.72 -67.936 2.7 30.969 58.784 -36.72 -68.332 (1) full strength driver characteristics 11.0 ibis : i/v characteristic s for input and output buffers
- 17 - rev. 1.2 november 2006 128m gddr sdram k4d261638i pulldown current (ma) pullup current (ma) voltage (v) minimum maximum minimum maximum 0.00000 0.1 1.332 1.716 -1.08 -1.144 0.2 4.752 6.776 -4.212 -5.94 0.3 7.992 11.704 -2.272 -10.56 0.4 11.008 16.456 -10.152 -15.092 0.5 13.968 21.07 6 -12.96 -19.36 0.6 16.74 25.784 -15.48 -23.496 0.7 19.08 30.052 -17.856 -27.588 0.8 21.24 34.144 -20.052 -31.284 0.9 23.04 37.884 -21.996 -35.024 1.0 24.516 41.404 -23.832 -38.368 1.1 25.596 44.308 -25.308 -41.492 1.2 26.388 46.772 -26.64 -44.352 1.3 26.964 48.664 -27.684 -46.816 1.4 27.36 50.248 -28.548 -49.06 1.5 27.648 51.348 -29.232 -50.864 1.6 27.828 52.14 -29.844 -52.448 1.7 28.008 52.756 -30.312 -53.812 1.8 28.188 53.196 -30.78 -54.956 1.9 28.296 53.19 6 -31.14 -55.88 2.0 28.44 53.768 -31.464 -56.672 2.1 28.548 53.988 -31.752 -57.376 2.2 28.62 54.164 -32.04 -57.992 2.3 28.728 54.296 -32.157 -58.476 2.4 28.8 54.472 -32.328 -59.004 2.5 28.908 54.604 -32.418 -59.444 2.6 28.953 54.692 -32.472 -59.84 2.7 28.998 54.824 -32.508 -60.28 (2) weak strength driver characteristics 11.0 ibis : i/v characteristic s for input and output buffers
- 18 - rev. 1.2 november 2006 128m gddr sdram k4d261638i pulldown current (ma) pullup current (ma) voltage (v) minimum maximum minimum maximum 0.00000 0.1 1.152 1.452 -0.972 -1.276 0.2 2.988 4.312 -2.916 -4.224 0.3 4.788 7.084 -4.824 -7.04 0.4 6.48 9.724 -6.516 -9.768 0.5 8.028 12.232 -8.172 -12.364 0.6 9.396 14.74 -9.756 -14.872 0.7 10.692 16.984 -11.16 -17.292 0.8 11.7 19.184 -12.42 -19.624 0.9 12.564 21.164 -13.572 -21.736 1.0 13.248 22.792 -14.544 -23.672 1.1 13.716 24.2 -15.372 -25.476 1.2 14.04 25.256 -16.056 -27.06 1.3 14.292 26.136 -16.632 -28.468 1.4 14.472 26.752 -17.1 -29.656 1.5 14.616 27.148 -17.496 -30.668 1.6 14.724 27.544 -17.82 -31.504 1.7 14.796 27.764 -18.108 -32.208 1.8 14.868 27.984 -18.324 -32.78 1.9 14.94 28.116 -18.54 -33.264 2.0 14.976 28.204 -18.756 -33.66 2.1 15.048 28.336 -18.9 -34.056 2.2 15.12 28.38 -19.08 -34.408 2.3 15.192 28.512 -19.224 -34.716 2.4 15.228 28.6 -19.332 -34.716 2.5 15.264 28.644 -19.431 -35.2 2.6 15.3 28.732 -19.611 -35.42 2.7 15.372 28.776 -19.692 -35.64 (3) matched strength driver characteristics 11.0 ibis : i/v characteristic s for input and output buffers
- 19 - rev. 1.2 november 2006 128m gddr sdram k4d261638i units : millimeters 0.30 0.08 0.65typ (0.71) 22.22 0.10 0.125 (0.80) 10.16 0.10 0 ~8 #1 #33 #66 #34 (1.50) (1.50) 0.65 0.08 1.00 0.10 1.20max (0.50) (0.50) (10.76) 11.76 0.20 (10 ) (10 ) +0.075 -0.035 (0.80) 0.10 max 0.075 max [] 0.05 min (10 ) (10 ) ( r 0 . 1 5 ) 0.210 0.05 0.665 0.05 ( r0.1 5 ) ( 4 ) ( r 0 . 2 5 ) ( r0.2 5 ) 0.45~0.75 0.25typ note 1. ( ) is reference 2. [ ] is ass ? y out quality 12.0 package dimensions (66pin tsop-ii)

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